Self-Checking and Fault-Tolerant Digital Design (Hardcover)

With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation.

Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.

Features:

• Introduces reliability theory and the importance of maintainability
• Presents coding and the construction of several error detecting and correcting codes
• Discusses in depth, the available techniques for fail-safe design of combinational circuits
• Details checker design techniques for detecting erroneous bits and encoding output of self-checking circuits
• Demonstrates how to design self-checking sequential circuits, including a technique for fail-safe state machine design

Authors:

Parag Lala is the Mullins Chair Professor at the University of Arkansas, where he teaches in the Department of Computer Science and Computer Engineering. He is well known for his research in the areas of VLSI system design and testing, self-checking (on-line testable) logic circuit design, field-programmable logic devices, fault-tolerant system design, and embryonics. Parag received his M.Sc. (Eng.) degree from King's College, London, and his Ph.D. from the City University of London. In 1998 he received his D.Sc. (Eng.) degree from the University of London. He is the author of Digital Circuit Testing and Testability.

Table of Contents:

Chapter 1 - Fundamentals of Reliability
Chapter 2 - Error Detecting and Correcting Codes
Chapter 3 - Self-Checking Combinational Logic Design
Chapter 4 - Self-Checking Checkers
Chapter 5 - Self-Checking Sequential Circuit Design
Chapter 6 - Fault-Tolerant Design
Appendix
Markov Models

Related Titles:

Computer Architecture & Design

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隨著VLSI晶片晶體管越來越小，今天的數位系統比以往更加複雜。這種增加的複雜性導致了更多的串擾、噪音和其他在正常操作期間產生的瞬態錯誤源。傳統的離線測試策略無法保證檢測到這些瞬態故障。而且，由於關鍵應用程序依賴於更快、更強大的晶片，必須建立容錯、自檢機制，以確保可靠的操作。

《自檢和容錯數位設計》廣泛探討了自檢設計技術，是唯一一本強調硬體容錯主要技術的書籍。VLSI設計課程的研究生以及實踐設計師將欣賞到這種平衡處理容錯概念和理論以及創建容錯系統所使用的實際技術。

特點：

• 介紹可靠性理論和可維護性的重要性
  


• 介紹編碼和構建多種錯誤檢測和修正編碼
  


• 詳細討論可組合電路失效安全設計的可用技術
  


• 詳細介紹檢查器設計技術，用於檢測錯誤位和編碼自檢電路的輸出
  


• 演示如何設計自檢序列電路，包括一種失效安全狀態機設計技術

作者:

Parag Lala是阿肯色大學的Mullins講座教授，他在計算機科學和計算機工程系任教。他以VLSI系統設計和測試、自檢（在線可測試）邏輯電路設計、可編程邏輯器件、容錯系統設計和胚胎學研究而聞名。Parag獲得了倫敦國王學院的M.Sc.（工程）學位，並在倫敦城市大學獲得了博士學位。1998年，他獲得了倫敦大學的D.Sc.（工程）學位。他是《數位電路測試和可測性》的作者。

目錄:

第1章 - 可靠性基礎

第2章 - 錯誤檢測和修正編碼

第3章 - 自檢組合邏輯設計

第4章 - 自檢檢查器

第5章 - 自檢序列電路設計

第6章 - 容錯設計

附錄

馬爾可夫模型

相關書籍:

計算機架構與設計

















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