Logic Design and Verification Using SystemVerilog (Revised)

Donald Thomas

  • 出版商: W. W. Norton
  • 出版日期: 2016-03-01
  • 售價: $2,580
  • 貴賓價: 9.5$2,451
  • 語言: 英文
  • 頁數: 336
  • 裝訂: Paperback
  • ISBN: 1523364025
  • ISBN-13: 9781523364022
  • 相關分類: Verilog邏輯設計 Logic-design
  • 立即出貨 (庫存 < 3)

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商品描述

SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: • students currently in an introductory logic design course that also teaches SystemVerilog, • designers who want to update their skills from Verilog or VHDL, and • students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design — these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book’s topics. The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning. Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.

商品描述(中文翻譯)

SystemVerilog是一種硬體描述語言,使設計師能夠在邏輯設計抽象的較高層次上工作,以應對當今集成電路和現場可編程閘陣列(FPGA)設計的日益複雜性。本書的大部分內容假設讀者具備基本的邏輯設計和軟體編程概念。本書的目標讀者包括:• 目前正在修讀介紹性邏輯設計課程並學習SystemVerilog的學生,• 希望從Verilog或VHDL更新技能的設計師,以及• 學習VLSI設計和高級邏輯設計課程(包括驗證和設計主題)的學生。本書以硬體描述語言和模擬的教程介紹開始。然後進一步介紹了組合和有限狀態機(FSM)設計的寄存器傳輸設計主題 - 這些主題與介紹性邏輯設計課程的主題相對應。本書涵蓋了FSM數據路徑設計及其接口的設計,包括SystemVerilog接口。然後介紹了更高級的主題,如編寫測試平台,包括使用斷言和功能覆蓋。全面的索引方便讀者查找書中的主題。本書的目標是以一種與介紹性和高級邏輯設計和驗證課程相輔相成的方式,介紹語言的廣泛特性,並為進一步學習奠定基礎。章末的問題解答和SystemVerilog示例的文本副本可從作者處獲得,詳情請參閱前言。