Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them(快遞進口)

Stuart Sutherland

  • 出版商: Springer
  • 出版日期: 2010-11-05
  • 售價: $4,800
  • 貴賓價: 9.5$4,560
  • 語言: 英文
  • 頁數: 236
  • 裝訂: Paperback
  • ISBN: 1441944028
  • ISBN-13: 9781441944023
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)

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商品描述

This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.

商品描述(中文翻譯)

這本書將幫助工程師們撰寫更好的Verilog/SystemVerilog設計和驗證程式碼,並更快地將數位設計推向市場。它展示了超過100個常見的Verilog和SystemVerilog語言編碼錯誤。每個例子都詳細解釋了錯誤的症狀、涵蓋錯誤的語言規則以及避免錯誤的正確編碼風格。這本書幫助數位設計和驗證工程師們識別並避免這些常見的編碼錯誤。其中許多錯誤非常微妙,可能會花費數小時或數天的工程時間來尋找和除錯。