Systemverilog for Verification: A Guide to Learning the Testbench Language Features, 3/e (Hardcover)

Chris Spear, Greg Tumbush

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商品描述

Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.

In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features,  including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include:

  • New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard
  • Descriptions of UVM features such as factories, the test registry, and the configuration database
  • Expanded code samples and explanations
  • Numerous samples that have been tested on the major SystemVerilog simulators

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.

 

商品描述(中文翻譯)

基於非常成功的第二版,這本擴展版的《SystemVerilog驗證指南:學習測試環境語言特性》教授了SystemVerilog語言的所有驗證特性,並提供了數百個例子來清楚解釋概念和基本原理。它包含了專職驗證工程師和學習這一寶貴技能的學生所需的材料。

在第三版中,作者Chris Spear和Greg Tumbush從如何驗證設計開始,然後利用這個背景來演示語言特性,包括不同風格的優缺點,讓讀者在選擇之間做出選擇。這本教科書包含了設計來增強學生對材料的理解的章末練習題。本版的其他特點包括:

- 2009年IEEE語言標準中關於靜態變量、打印格式指定符和DPI的新章節
- UVM特性的描述,如工廠、測試註冊表和配置數據庫
- 擴展的代碼示例和解釋
- 在主要SystemVerilog模擬器上經過測試的大量示例

《SystemVerilog驗證指南:學習測試環境語言特性,第三版》適用於本科或研究生水平的一學期SystemVerilog課程。這個新版的許多改進都是通過數百名讀者提供的反饋來編制的。