Formal Verification: An Essential Toolkit for Modern VLSI Design, 2/e (美國原版)

Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.

New sections cover advanced techniques, and a new chapter, The Road To Formal Signoff, emphasizes techniques used when replacing simulation work with Formal Verification. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.

《正式驗證：現代VLSI設計的必備工具包，第二版》提供了實用的設計和驗證方法，並提供實用建議，幫助工程師將這些技術融入他們的工作中。正式驗證（FV）使設計師能夠直接分析和數學探索註冊傳輸層（RTL）設計的質量或其他方面，而無需使用模擬。這可以減少驗證設計所需的時間，更快地達到最終的製造設計。本書在基本的SystemVerilog知識基礎上，揭示了FV的神秘面紗，並介紹了將其引入主流設計和驗證流程中的實際應用。

新的章節涵蓋了高級技術，而新的一章《正式簽署之路》則強調了在替代模擬工作時使用的正式驗證技術。閱讀本書後，讀者將能夠在組織中引入FV，以有效地應用提高設計和驗證生產力的FV技術。