Boolean Circuit Rewiring: Bridging Logical and Physical Designs Hardcover

Tak-Kei Lam, Wai-Chung Tang, Xing Wei, Yi Diao, David Yu-Liang Wu

商品描述

Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications

Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs.

  • Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field
  • Provides complete coverage of rewiring from an introductory to intermediate level
  • Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples
  • Readers can directly apply the described techniques to real-world VLSI design issues
  • Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and “set of pairs of functions to be distinguished” (SPFD) based rewiring are also discussed

A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.

商品描述(中文翻譯)

展示了一種技術,可以實現超過95%的重線速率,從而使得深亞微米晶片在工業應用中能夠被採用。

邏輯合成是半導體行業現代數字IC設計過程中的重要組成部分。本書討論了一種稱為“重線”(rewiring)的邏輯合成技術及其在可重線性方面的最新技術進展。自1993年以來,重線技術已經在學術研究中出現,目前市場上還沒有一本系統全面地討論這種重線技術的書籍。作者們重點介紹了邏輯轉換技術,尤其是重線技術。數十年來,由於對線路的理想觀點和其在電路性能中的微不足道的作用,人們忽視了線路對邏輯結構的影響。然而,在當今的半導體技術中,線路是電路性能退化的主要因素,邏輯合成引擎可以通過基於線路的轉換來改善這一問題。本書介紹了基於自動測試模式生成(ATPG)的重線技術,這些技術最近在VLSI/SOC設計的邏輯合成/驗證領域中非常活躍。

本書是由該領域的領先研究人員撰寫的,全面介紹了半導體重線技術。從入門到中級水平,全面涵蓋了重線技術。本書將重線解釋為布爾邏輯合成的一種靈活技術,介紹了布爾電路轉換和測試的概念,並提供了相應的示例。讀者可以直接將所描述的技術應用於實際的VLSI設計問題。本書重點介紹了基於自動測試模式生成(ATPG)的重線方法,同時還討論了一些非ATPG方法,如基於圖形的替代線路(GBAW)和基於“需要區分的一組函數對”(SPFD)的重線。

本書對於VLSI和SoC設計的研究人員和研究生,以及數字設計工程師、EDA軟件開發人員和設計自動化專家,尤其是在邏輯電路的合成和優化方面的專家,都是一個寶貴的資源。