Introduction to Systemverilog (美國原版)

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs.

• Provides comprehensive coverage of the entire IEEE standard SystemVerilog language;
• Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features;
• Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online;
• Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs.

This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have!

The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers.

Mark Glasser

Cerebras Systems

本書提供了一個實踐導向的指南，介紹了整個IEEE標準1800 SystemVerilog語言。讀者將從逐步學習語言和方法論細微差異的方法中受益，這將使他們能夠設計和驗證複雜的ASIC/SoC和CPU芯片。作者涵蓋了語言的整個範譜，包括隨機約束、SystemVerilog斷言、功能覆蓋、類、檢查器、接口和數據類型等語言特性。本書由一位經驗豐富的ASIC/SoC/CPU和FPGA設計的專業用戶撰寫，通過易於理解的示例、模擬日誌和來自實際項目的應用來解釋每個概念。讀者將能夠應對百萬門ASIC設計的複雜任務。

本書提供了對整個IEEE標準SystemVerilog語言的全面覆蓋；
涵蓋了重要主題，如約束隨機驗證、SystemVerilog類、斷言、功能覆蓋、數據類型、檢查器、接口、過程和程序等語言特性；
使用易於理解的示例和模擬日誌；示例可模擬並可在線提供；
由一位經驗豐富的ASIC/SoC/CPU和FPGA設計的專業用戶撰寫。

這是一本相當全面的著作。撰寫這本書肯定花了很長時間。我真的很喜歡作者對SystemVerilog結構的詳細解析，包括示例代碼和模擬日誌。例如，有一章專門介紹了數組，另一章專門介紹了隊列 - 這非常棒！

語言參考手冊（LRM）非常密集且難以作為學習語言的教材。這本書以無法在LRM中實現的詳細程度解釋了語義。這是本書的優勢。對於初學者和經驗豐富的程序員來說，這將是一本優秀的書籍和方便的參考資料。

Mark Glasser
Cerebras Systems

Ashok Mehta is an ASIC/CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on SystemVerilog Assertions and Functional Coverage and second on ASIC Functional Design Verification - A guide to technologies and methodologies. His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.

Ashok Mehta是一位在半導體行業擁有超過30年經驗的ASIC/CPU設計和驗證工程師。他曾在DEC、Data General、Intel、Applied Micro和TSMC等公司工作。他是Verilog技術小組的早期成員之一。他在ASIC和3DIC設計和驗證領域擁有19項美國專利。他還是兩本受歡迎的書籍的作者，一本是關於SystemVerilog斷言和功能覆蓋，另一本是關於ASIC功能設計驗證 - 技術和方法論指南。他目前的興趣包括3DIC半導體設計驗證、系統級建模（虛擬平台）和一般驗證方法論。