ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies (Hardcover)

Ashok B. Mehta

  • 出版商: Springer
  • 出版日期: 2017-07-07
  • 售價: $6,160
  • 貴賓價: 9.5$5,852
  • 語言: 英文
  • 頁數: 328
  • 裝訂: Hardcover
  • ISBN: 3319594176
  • ISBN-13: 9783319594170
  • 海外代購書籍(需單獨結帳)

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商品描述

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon.  The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail.  He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.

 

商品描述(中文翻譯)

本書詳細描述了創建全面、功能性的設計驗證策略和環境所需的所有技術和方法,以應對確保首次通過的工作硅片的最困難的任務。作者首先以高層次概述了所有驗證子領域,深入到足夠的細節,讓工程師能夠理解該領域,然後詳細描述了行業標準技術,如UVM(通用驗證方法學)、SVA(SystemVerilog斷言)、SFC(SystemVerilog功能覆蓋)、CDV(覆蓋驅動驗證)、低功耗驗證(統一功耗格式UPF)、AMS(模擬混合信號)驗證、虛擬平台TLM2.0/ESL(電子系統級方法學)、靜態形式驗證、邏輯等效性檢查(LEC)、硬件加速、硬件仿真、硬件/軟件協同驗證、虛擬平台上的功耗性能面積(PPA)分析,從算法/ESL到RTL的重用方法學,以及其他整體方法學。