Real World FPGA Design with Verilog
暫譯: 實務FPGA設計與Verilog

Ken Coffman

Real World FPGA Design with Verilog
  • 出版商: Prentice Hall
  • 出版日期: 1999-12-08
  • 售價: $1,260
  • 貴賓價: 9.8 折 $1,235
  • 語言: 英文
  • 頁數: 291
  • 裝訂: Paperback
  • ISBN: 0130998516
  • ISBN-13: 9780130998514
  • 相關分類: FPGA、Verilog

    • 已絕版

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商品描述

Description:

Real World Verilogguides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages.KEY TOPICS:Start by walking a typical Verilog design all the way to silicon. Next, review basic Verilog syntax; design partitioning and synthesis issues; simulation and testing; combinatorial and sequential designs; black boxes and advanced simulation. You'll find irreverent yet rigorous coverage of what it really takes to translate HDL code into hardware -- and how to avoid the pitfalls that can occur along the way. Ken Coffman's no-frills, real-world design techniques can improve the stability and reliability of virtually any design. The accompanying CD-ROM includes working demo and student versions of popular Verilog, FPGA, synthesis, and simulation tools.MARKET:For anyone involved in Verilog design, especially entry-to-mid-level digital hardware designers.

 

Table of Contents:

1. Verilog Design in the Real World.

Trivial Overheat Detector Example. Synthesizable Verilog Elements. Verilog Hierarchy. Built-In Logic Primitives. Latches and Flipflops. Blocking and Nonblocking Assignments. Miscellaneous Verilog Syntax Items.

2. Digital Design Strategies and Techniques.

Design Processing Steps. Analog Building Blocks for Digital Primitives. Using a LUT to Implement Logic Functions. Discussion of Design Processing Steps. Synchronous Logic Rules. Clocking Strategies. Logic Minimization. What Does the Synthesizer Do? Area/Delay Optimization.

3. A Digital Circuit Toolbox.

Verilog Hierarchy Revisited. Tristate Signals and Busses. Bidirectional Busses. Priority Encoders. Area/Speed Optimization in Synthesis. Trade-off Between Operating Speed and Latency. Delays in FPGA Logic Elements. State Machines. Adders. Subtractors. Multipliers.

4. More Digital Circuits: Counters, RAMs, and FIFOs.

Ripple Counters. Johnson Counters. Linear Feedback Shift Registers. Cyclic Redundancy Checksums. ROM. RAM. FIFO Notes.

5. Verilog Test Fixtures.

Compiler Directives. Automated Testing.

6. Real World Design: Tools, Techniques, and Trade-offs.

Compiling with LeonardoSpectrum. Complete Design Flow, 8-Bit Equality Comparator. 8-Bit Equality Comparator with Hierarchy. Optimization Options In the Xilinx Environment. Mapping Options. Logic Level Timing Report/Post Layout Timing Report. VHDL/Verilog Simulation Options. Other Design Manager Tools.

7. A Look at Competing Architectures.

Factors that Determine Integrated Circuit Pricing. FPGA Device Design. FPGA Technology Selection Checklist. Xilinx FPGA Architectures. Altera CPLD Architectures.

8. Libraries, Reusable Modules, and IP.

Keys to Increased Productivity. Library Elements. Structural Coding Style. A Small Diversion to Compare a Schematic to a Verilog Design. Using LogiBLOX Module Generator. Design Reuse, Reusing Your Own Code. Buying IP Designs. Summing Up.

9. Designing for ASIC Conversion.

HardWire Devices. Semicustom Devices. Design Rules for ASIC Conversion. Synchronous Design Rules. Oscillators. Delay Lines. The Language of Test. Print-on-Change Test Vectors. Afterword-A Look into the Future. Resources. Glossary and Acronyms. Bibliography.

Index.

The Author

商品描述(中文翻譯)

描述：


實務中的 Verilog引導您克服與使用 Verilog 設計 FPGA 和 ASIC 相關的每一個關鍵挑戰，Verilog 是全球領先的硬體設計語言之一。關鍵主題：首先，從一個典型的 Verilog 設計開始，一直到矽片。接下來，回顧基本的 Verilog 語法；設計分區和綜合問題；模擬和測試；組合邏輯和時序邏輯設計；黑盒和進階模擬。您將發現對於將 HDL 代碼轉換為硬體所需的真實要求的無畏而嚴謹的探討，以及如何避免過程中可能出現的陷阱。Ken Coffman 的簡約實務設計技術可以改善幾乎任何設計的穩定性和可靠性。隨書附贈的 CD-ROM 包含流行的 Verilog、FPGA、綜合和模擬工具的工作示範和學生版本。市場：適合任何參與 Verilog 設計的人，特別是入門到中階的數位硬體設計師。


 


目錄：


1. 實務中的 Verilog 設計。



微不足道的過熱檢測器範例。可綜合的 Verilog 元件。Verilog 階層。內建邏輯原語。鎖存器和觸發器。阻塞和非阻塞賦值。其他 Verilog 語法項目。


2. 數位設計策略和技術。



設計處理步驟。數位原語的類比建構塊。使用 LUT 實現邏輯函數。設計處理步驟的討論。同步邏輯規則。時鐘策略。邏輯最小化。綜合器的功能是什麼？面積/延遲優化。


3. 數位電路工具箱。



重新檢視 Verilog 階層。三態信號和總線。雙向總線。優先編碼器。綜合中的面積/速度優化。操作速度和延遲之間的權衡。FPGA 邏輯元件中的延遲。狀態機。加法器。減法器。乘法器。


4. 更多數位電路：計數器、RAM 和 FIFO。



波紋計數器。約翰遜計數器。線性反饋移位暫存器。循環冗餘檢查和校驗和。ROM。RAM。FIFO 註解。


5. Verilog 測試裝置。



編譯器指令。自動化測試。


6. 實務設計：工具、技術和權衡。



使用 LeonardoSpectrum 編譯。完整的設計流程，8 位元相等比較器。具有階層的 8 位元相等比較器。在 Xilinx 環境中的優化選項。映射選項。邏輯級時序報告/後佈局時序報告。VHDL/Verilog 模擬選項。其他設計管理工具。


7. 競爭架構的概覽。



決定集成電路定價的因素。FPGA 設計。FPGA 技術選擇檢查表。Xilinx FPGA 架構。Altera CPLD 架構。


8. 函式庫、可重用模組和 IP。



提高生產力的關鍵。函式庫元素。結構化編碼風格。小小的偏離，將原理圖與 Verilog 設計進行比較。使用 LogiBLOX 模組生成器。設計重用，重用您自己的代碼。購買 IP 設計。總結。


9. 為 ASIC 轉換設計。



硬體設備。半定制設備。ASIC 轉換的設計規則。同步設計規則。振盪器。延遲線。測試的語言。變更時打印測試向量。後記—展望未來。資源。術語表和縮寫。參考書目。


索引。

作者

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