Writing Testbenches using SystemVerilog (Hardcover)

Janick Bergeron

  • 出版商: Springer
  • 出版日期: 2006-02-10
  • 售價: $7,780
  • 貴賓價: 9.5$7,391
  • 語言: 英文
  • 頁數: 412
  • 裝訂: Hardcover
  • ISBN: 1846280230
  • ISBN-13: 9780387292212
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)

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Description

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.

Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.

Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model.

Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.

Written for:
Design automation verification engineers
 
Table of contents

What is Verification?.- Verification Technologies.- The Verification Plan.- High-Level Modeling.- Stimulus and Response.- Architecting Testbenches.- Simulation Management.- Appendix A: Coding Guidelines.- Appendix B: Glossary.

商品描述(中文翻譯)

描述

驗證常常以臨時的方式進行。視覺檢查模擬結果已不再可行,而有向測試案例的方法已達到極限。摩爾定律要求在功能驗證方法論中進行生產力革命。

《使用SystemVerilog編寫測試環境》提供了一個明確的驗證流程藍圖,旨在使用SystemVerilog語言實現首次成功。從模擬器到源代碼管理工具,從規格到功能覆蓋,從輸入和輸出到高層抽象,從接口到總線功能模型,從事務到自檢測測試環境,從有向測試案例到受限隨機生成器,從行為模型到回歸套件,本書涵蓋了所有內容。

《使用SystemVerilog編寫測試環境》介紹了作為SystemVerilog的一部分添加到Verilog語言中的許多功能驗證特性。介面、虛擬模塊端口、類、程序塊、時鐘塊和其他SystemVerilog特性在一個連貫的驗證方法論和使用模型中被引入。

《使用SystemVerilog編寫測試環境》向讀者介紹了現代可擴展驗證方法論的所有要素。它是《SystemVerilog驗證方法論手冊》中詳細介紹的驗證方法論的引言和前奏。

寫給:

- 設計自動化驗證工程師

目錄

- 什麼是驗證?- 驗證技術- 驗證計劃- 高層建模- 刺激和響應- 測試環境架構- 模擬管理- 附錄A:編碼指南- 附錄B:詞彙表