Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications

This book provides a composite solution for optimal logic designs for Quantum-Dot Cellular Automata based circuits. It includes the basics of new logic functions and novel digital circuit designs, quantum computing with QCA, new trends in quantum and quantum-inspired algorithms and applications, and algorithms to support QCA designers.

Futuristic Developments in Quantum-Dot Cellular Automata Circuits for Nanocomputing includes QCA-based new nanoelectronics architectures that help in improving the logic computation and information flow at physical implementation level. The book discusses design methodologies to obtain an optimal layout for some of the basic logic circuits considering key metrics such as wire delays, cell counts, and circuit area that help in improving the logic computation and information flow at physical implementation level. Examines several challenges toward QCA technology like clocking mechanism, floorplan which would facilitate manufacturability, Electronic Design Automation (EDA) tools for design and fabrication like simulation, synthesis, testing etc.

The book is intended for students and researchers in electronics and computer disciplines who are interested in this rapidly changing field under the umbrella of courses such as emerging nanotechnologies and its architecture, low-power digital design. The work will also help the manufacturing companies/industry professionals, in nanotechnology and semiconductor engineers in the development of low power quantum computers.

本書提供了一個針對基於量子點細胞自動機的電路的最佳邏輯設計的綜合解決方案。它包括新邏輯功能和新穎數字電路設計的基礎知識，以及使用QCA進行量子計算、量子和量子啟發算法和應用的新趨勢，以及支持QCA設計師的算法。

《納米計算的量子點細胞自動機電路的未來發展》包括基於QCA的新型納米電子架構，有助於改善邏輯計算和信息流在物理實現層面上的表現。本書討論了設計方法論，以獲得一些基本邏輯電路的最佳佈局，考慮到線路延遲、單元數量和電路面積等關鍵指標，有助於改善邏輯計算和信息流在物理實現層面上的表現。還探討了幾個關於QCA技術的挑戰，如時鐘機制、平面圖，這將有助於可製造性，以及用於設計和製造的電子設計自動化（EDA）工具，如模擬、合成、測試等。

本書面向對電子和計算機學科感興趣的學生和研究人員，他們對這個在新興納米技術和其架構、低功耗數字設計等課程範疇下迅速變化的領域感興趣。這項工作還將幫助製造公司/行業專業人士，在納米技術和半導體工程師在低功耗量子計算機的開發方面。

Dr. Trailokya Nath Sasamal is currently working as Assistant Professor in the Department of Electronics & Communication Engineering at National Institute of Technology, Kurukshetra, India since August 2013. He has more than 11 years research and teaching experience in various University systems of India. Dr. Sasamal has obtained Ph.D. degree from the Department of Electronics & Communication Engineering, NIT Kurukshetra, Haryana. He obtained his M. Tech degree in Electronics Engineering from Indian Institute of Technology, Banaras Hindu University, Varanasi, India. He obtained his B. Tech degree in Electronics & Telecommunication from the KEC, Bhubaneswar, India, in 2007. He has presented and published over 60 research papers in reputed journals and various national and international conferences. His research interests include Quantum-dot Cellular Automata, Reversible logic, and new architectures for emerging nano-devices. He is the author of the book "Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective", published in Springer. He is also involved in reviewing processes in different journals and conferences such as; IEEE, IET, JCSC, IETE, DSJ etc.

Dr. Hari Mohan Gaur is currently working with the School of Computer Science Engineering and Technology at Bennett University, Greater Noida, India. He obtained Ph.D from National Institute of Technology Kurukshetra (NIT-KKR) in Reversible and Quantum Computation. Hari Mohan Gaur has more than 15 years of experience in academic, research and administrative capacities. He is a distinguished Researcher, well known in Academic Fraternity for his interdisciplinary research in the areas of Quantum Computation, Fault Tolerant Digital Design, IOT and Data Security in Cloud Environment. Dr. Gaur holds the credit of contribution in several quality research journals of international repute published by IEEE, ACM, IET, Elsevier, etc. He is having a wide exposure of handling research proposals, international conferences, Training and Faculty Development Programs. He is involved in a joint research group involving eminent professors from top universities of US, UK, Japan, Taiwan and Malaysia. He has also been editor and reviewer of several international journals and is a member of IEEE since 2017.

Prof. Ashutosh Kumar Singh is an esteemed researcher and academician in the domain of Electrical and Computer engineering. Currently, he is working as a Professor; Department of Computer Applications; National Institute of Technology; Kurukshetra, India. He has more than 20 years research, teaching and administrative experience in various University systems of the India, UK, Australia and Malaysia. Dr. Singh obtained his Ph. D. degree in Electronics Engineering from Indian Institute of Technology-BHU, India; Post Doc from Department of Computer Science, University of Bristol, United Kingdom and Charted Engineer from United Kingdom. He is the recipient of Japan Society for the Promotion of Science (JSPS) fellowship for visit in University of Tokyo and other universities of Japan. His research area includes Verification, Synthesis, Design and Testing of Digital Circuits, Predictive Data Analytics, Data Security in Cloud, Web Technology. He has more than 350 publications till now which includes peer reviewed journals, books, conferences, book chapters and news magazines in these areas. He has co-authored eight books including "Web Spam Detection Application using Neural Network", "Digital Systems Fundamentals" and "Computer System Organization & Architecture". Prof. Singh has worked as principal investigator/investigator for six sponsored research projects and was a key member on a project from EPSRC (United Kingdom) entitled "Logic Verification and Synthesis in New Framework". Dr. Singh has visited several countries including Australia, United Kingdom, South Korea, China, Thailand, Indonesia, Japan and USA for collaborative research work, invited talks and to present his research work. He had been entitled for 15 awards such as Merit Awards-2003 (Institute of Engineers), Best Poster Presenter-99 in 86th Indian Science Congress held in Chennai, INDIA, Best Paper Presenter of NSC'99 INDIA and Bintulu Development Authority Best Postgraduate Research Paper Award for 2010, 2011, 2012.

Prof. Xiaoqing Wen (Fellow, IEEE) received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at the University of Wisconsin, Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its Chief Technology Officer until 2003. In 2004, he joined the Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He founded the Dependable Integrated Systems Research Center in 2015 and served as its Director until 2017. He has co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). He holds 43 U.S. patents and 14 Japanese patents on VLSI testing. His research interests include VLSI test, diagnosis, and testable design. He is a member of the IEICE, the IPSJ, and the REAJ. He received the 2008 IEICE-ISS Best Paper Award for his pioneering work on X-filling-based low-capture-power test generation. He has/is served/serving as an Associate Editor for the IEEE Transactions on Computer- Aided Design, the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and the Journal of Electronic Testing: Theory and Applications

Dr. Trailokya Nath Sasamal目前擔任印度國立科技學院（National Institute of Technology）電子與通訊工程系的助理教授，自2013年8月起。他在印度各大學系統擁有超過11年的研究和教學經驗。Sasamal博士在哈里亞納邦國立科技學院（NIT Kurukshetra）的電子與通訊工程系獲得博士學位。他在印度班拉斯印度大學（Indian Institute of Technology, Banaras Hindu University）的電子工程系獲得碩士學位。他在2007年在印度布巴內斯瓦爾科技學院（KEC）的電子與通訊工程系獲得學士學位。他在知名期刊和各國家和國際會議上發表和發表了60多篇研究論文。他的研究興趣包括量子點細胞自動機、可逆邏輯和新興納米器件的新架構。他是Springer出版的書籍《基於量子點細胞自動機的數字邏輯電路：設計觀點》的作者。他還參與了不同期刊和會議的審查過程，如IEEE、IET、JCSC、IETE、DSJ等。

Dr. Hari Mohan Gaur目前在印度Greater Noida的Bennett大學計算機科學工程和技術學院工作。他在可逆和量子計算方面從印度國立科技學院Kurukshetra（NIT-KKR）獲得博士學位。Hari Mohan Gaur在學術、研究和行政方面擁有超過15年的經驗。他是一位傑出的研究者，在量子計算、容錯數字設計、物聯網和雲環境中的數據安全等領域的跨學科研究方面享有盛譽。Gaur博士在IEEE、ACM、IET、Elsevier等國際知名期刊上發表了多篇優質研究論文。他在處理研究提案、國際會議、培訓和教師發展計劃方面具有廣泛的經驗。他參與了一個由美國、英國、日本、台灣和馬來西亞頂尖大學的傑出教授組成的聯合研究小組。他還擔任過多個國際期刊的編輯和審稿人，自2017年起成為IEEE的會員。

Ashutosh Kumar Singh教授是電氣和計算機工程領域的傑出研究者和學者。目前，他在印度國立科技學院（National Institute of Technology）的計算機應用系擔任教授。他在印度、英國、澳大利亞和馬來西亞的各大學系統中擁有超過20年的研究、教學和行政經驗。Singh博士在印度班拉斯印度大學（Indian Institute of Technology-BHU）的電子工程系獲得博士學位，並在英國布里斯托大學（University of Bristol）的計算機科學系進行博士後研究，並獲得英國特許工程師資格。他曾獲得日本學術振興會（JSPS）的獎學金，訪問東京大學和日本其他大學。他的研究領域包括數字電路的驗證、合成、設計和測試，預測性數據分析，雲端數據安全，網絡技術等。他迄今為止發表了350多篇論文，包括同行評審的期刊、書籍、會議、書籍章節和新聞雜誌。他合著了八本書，包括《使用神經網絡的網絡垃圾郵件檢測應用》、《數字系統基礎》和《計算機系統組織與架構》。Singh教授曾擔任六個贊助研究項目的主要研究員/研究員，並是英國工程和自然科學研究委員會（EPSRC）的一個名為“新框架中的邏輯驗證和合成”的項目的關鍵成員。Singh博士曾訪問過澳大利亞、英國、韓國、中國、泰國、印尼、日本和美國等多個國家進行合作研究工作，並自2017年起成為IEEE的會員。