Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers (Paperback)

content<p> <p style="line-height: 150%; margin: 6pt 0in;" class="MsoNormal"><em><span style="color: #222222;">Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers</span></em> provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor. </p> <p style="line-height: 150%; margin: 6pt 0in;" class="MsoNormal">Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them. </p> <p style="line-height: 150%; margin: 6pt 0in;" class="MsoNormal">In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.<o:o:p></o:o:p></p> </p> <h3>What you’ll learn</h3><p style="line-height: 150%; margin: 6pt 0in;" class="MsoNormal"> </p> <ul> <li><span style="line-height: 150%;">How to calculate theoretical Gigaflops and bandwidth numbers on the hardware and measure them through code segment</span> </li> <li><span style="line-height: 150%; font-family: calibri,sans-serif; font-size: 11pt;">How to estimate latencies in fetching data from different cache hierarchies, including memory subsystems</span> </li> <li><span style="line-height: 150%; font-family: calibri,sans-serif; font-size: 11pt;">How to measure PCIe bus bandwidth between the host and coprocessor</span> </li> <li><span style="line-height: 150%; font-family: calibri,sans-serif; font-size: 11pt;">How to exploit power management and reliability features built into the hardware</span> </li> <li><span style="line-height: 150%; font-family: calibri,sans-serif; font-size: 11pt;">How to select and manipulate the best tools to tune particular Xeon Phi applications</span> </li> <li><span style="line-height: 150%; font-family: calibri,sans-serif; font-size: 11pt;">Algorithms and data structures for optimizing Xeon Phi performance</span> </li> <li><span style="line-height: 150%; font-family: calibri,sans-serif; font-size: 11pt;">Case studies of real-world Xeon Phi technical computing applications in molecular dynamics and financial simulations</span> </li> </ul> <o:o:p></o:o:p> <p> </p> <p style="line-height: 150%; margin: 6pt 0in;" class="MsoNormal"> </p> <h3>Who this book is for</h3> <p> <p class="MsoBodyText">This book is for developers wishing to design and develop technical computing applications to achieve the highest performance available in the Intel Xeon Phi coprocessor hardware. It provides a solid base on the coprocessor architecture, as well as algorithm and data structure case studies for Xeon Phi coprocessor. The book may also be of interest to students and practitioners in computer engineering as a case study for massively parallel core microarchitecture of modern day processors.</p> </p> <h3>Table of Contents</h3><p class="MsoNormal">1.  Introduction to Xeon Phi Architecture <br /> <br /> 2.  Programming Xeon Phi<br /> <br /> 3.  Xeon Phi Vector Architecture and Instruction Set<br /> <br /> 4.  Xeon Phi Core Microarchitecture<br /> <br /> 5.  Xeon Phi Cache and Memory Subsystem<br /> <br /> 6.  Xeon Phi PCIe Bus Data Transfer and Power Management<br /> <br /> 7.  Xeon Phi System Software<br /> <br /> 8.  Xeon Phi Application Development Tools<br /> <br /> 9.  Xeon Phi Application Design and Implementation Considerations<br /> <br /> 10.  Application Performance Tuning on Xeon Phi<br /> <br /> 11.  Algorithms and Data Structures for Xeon Phi<br /> <br /> 12.  Xeon Phi Application Development on Windows OS<br /> <br /> 13.  OpenCL on Intel<br /> <br /> 14.  Shared Memory Programming on Intel Xeon Phi</p> <p> </p>sourceProduct Description

《Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers》是一本針對應用程式開發人員提供全面介紹和深入研究Intel Xeon Phi協處理器架構及相應並行資料結構工具和演算法的指南。本書還探討了可以進行的源代碼級優化，以充分利用處理器的強大功能。

Xeon Phi是世界上最快的商用超級計算機的核心，得益於Intel Xeon Phi處理器和Xeon Phi協處理器的大規模並行計算能力，該計算機在2013年達到了33.86 teraflops的基準性能。要在實際應用中實現如此出色的性能，需要對硬件組件、Xeon Phi核心和運行在其上的應用程序之間的複雜交互有深入的理解。

在這本書中，Intel Xeon Phi協處理器開發和應用程序優化方面的專家Rezaur Rahman詳細介紹了與應用程式開發實踐相關的Xeon Phi核心設計特性，例如向量單元、硬件多線程、緩存層次結構和主機到協處理器的通信通道。在此基礎上，他向開發人員展示如何通過選擇、部署和優化可用的演算法和資料結構來解決實際的技術計算問題，以適應Xeon Phi的硬件特性。通過Rahman的實用描述和大量代碼示例，讀者將獲得對Xeon Phi向量指令集和Xeon Phi微架構的實際了解，其中核心可以並行執行512位指令流。

你將學到什麼:
- 如何在硬件上計算理論上的Gigaflops和帶寬數字，並通過代碼段測量它們
- 如何估計從不同緩存層次（包括記憶體子系統）中提取數據的延遲時間
- 如何測量主機和協處理器之間的PCIe總線帶寬
- 如何利用硬件內置的功耗管理和可靠性功能
- 如何選擇和操作最佳工具來調整特定的Xeon Phi應用程式
- 優化Xeon Phi性能的演算法和資料結構
- 分子動力學和金融模擬等實際Xeon Phi技術計算應用的案例研究