Interconnection Networks (Hardcover)
Jose Duato, Sudhakar Yalamanchili, Lionel Ni
- 出版商: Morgan Kaufmann
- 出版日期: 2002-07-29
- 售價: $3,810
- 貴賓價: 9.5 折 $3,620
- 語言: 英文
- 頁數: 624
- 裝訂: Hardcover
- ISBN: 1558608524
- ISBN-13: 9781558608528
-
其他版本:
Interconnection Networks
已絕版
買這商品的人也買了...
-
$680$537 -
$2,210$2,100 -
$1,029Operating Systems: Internals and Design Principles, 4/e
-
$980$774 -
$970Introduction to Algorithms, 2/e
-
$1,710$1,625 -
$880$695 -
$1,274Computer Architecture: A Quantitative Approach, 3/e(精裝本)
-
$1,860$1,767 -
$580$458 -
$590$466 -
$690$538 -
$750$675 -
$560$504 -
$480$379 -
$750$593 -
$780$616 -
$590$460 -
$3,010$2,860 -
$700$686 -
$1,029Principles and Practices of Interconnection Networks (Hardcover)
-
$1,100$1,078 -
$600$480 -
$650$585 -
$780$663
相關主題
商品描述
The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems.
Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems.
In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature
Foreword
Foreword to the First Printing
Preface
Chapter 1 - Introduction
Chapter 2 - Message Switching Layer
Chapter 3 - Deadlock, Livelock, and Starvation
Chapter 4 - Routing Algorithms
Chapter 5 - CollectiveCommunicationSupport
Chapter 6 - Fault-Tolerant Routing
Chapter 7 - Network Architectures
Chapter 8 - Messaging Layer Software
Chapter 9 - Performance Evaluation
Appendix A - Formal Definitions for Deadlock Avoidance
Appendix B - Acronyms
References
Index