Verilog by Example: A Concise Introduction for FPGA Design (Paperback)
Blaine Readler
- 出版商: Full Arc Press
- 出版日期: 2011-04-19
- 售價: $898
- 貴賓價: 9.5 折 $853
- 語言: 英文
- 頁數: 124
- 裝訂: Paperback
- ISBN: 0983497303
- ISBN-13: 9780983497301
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相關分類:
FPGA、Verilog
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商品描述
A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.
