Verilog by Example: A Concise Introduction for FPGA Design (Paperback)
暫譯: Verilog 實例解析：FPGA 設計的簡明入門
Blaine Readler
- 出版商: Full Arc Press
- 出版日期: 2011-04-19
- 售價: $1,040
- 貴賓價: 9.8 折 $1,019
- 語言: 英文
- 頁數: 124
- 裝訂: Paperback
- ISBN: 0983497303
- ISBN-13: 9780983497301
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相關分類:
FPGA、Verilog
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商品描述
A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.
商品描述(中文翻譯)
本書是為已熟悉數位設計基礎的學生和實務工程師所編寫的實用入門書，逐步發展對 Verilog 硬體描述語言的工作理解，並使用易於理解的範例。從一個簡單但可行的設計範例開始，逐漸引入語言中越來越複雜的基本概念，直到揭示 Verilog 的所有主要特性。內容涵蓋狀態機、模組化設計、基於 FPGA 的記憶體、時鐘管理、專用 I/O 以及模擬技術的介紹。目標是準備讀者設計實際的 FPGA 解決方案。本書中使用的所有範例程式碼均可在線獲得。正如 Strunk 和 White 的《風格的要素》對英語所做的，VERILOG BY EXAMPLE 對 FPGA 設計所做的貢獻。
