Formal Verification: An Essential Toolkit for Modern VLSI Design (美國原版)

Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar

  • 出版商: Morgan Kaufmann
  • 出版日期: 2015-08-14
  • 定價: $3,400
  • 售價: 8.0$2,720
  • 語言: 英文
  • 頁數: 408
  • 裝訂: Paperback
  • ISBN: 0128007273
  • ISBN-13: 9780128007273
  • 相關分類: VLSI
  • 立即出貨(限量) (庫存=1)

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商品描述

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.

  • Learn formal verification algorithms to gain full coverage without exhaustive simulation
  • Understand formal verification tools and how they differ from simulation tools
  • Create instant test benches to gain insight into how models work and find initial bugs
  • Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems

商品描述(中文翻譯)

《正式驗證:現代VLSI設計的必備工具包》提供了實用的設計和驗證方法,並提供實用建議,幫助工程師將這些技術融入他們的工作中。正式驗證(FV)使設計師能夠直接分析和數學探索註冊傳輸層(RTL)設計的質量或其他方面,而無需使用模擬。這可以減少驗證設計所需的時間,更快地達到最終的製造設計。本書在基本的SystemVerilog知識基礎上,揭示了FV的神秘面紗,並介紹了將其引入英特爾和其他公司主流設計和驗證流程的實際應用。閱讀本書後,讀者將能夠在組織中引入FV,並有效地應用FV技術以提高設計和驗證效率。


  • 學習正式驗證算法,實現全面覆蓋而無需進行耗時的模擬

  • 了解正式驗證工具及其與模擬工具的區別

  • 創建即時測試平台,深入了解模型的工作原理並找到初始錯誤

  • 從英特爾內部人員分享他們辛苦獲得的知識和解決複雜設計問題的解決方案中學習