Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6/e (GE-Paperback)
M. Morris Mano , Michael Ciletti
- 出版商: Pearson FT Press
- 出版日期: 2018-06-01
- 定價: $1,380
- 售價: 9.8 折 $1,352
- 語言: 英文
- 頁數: 710
- ISBN: 1292231165
- ISBN-13: 9781292231167
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相關分類:
Verilog、電路學 Electric-circuits
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相關翻譯:
數位邏輯設計, 6/e (Mano: Digital Design, 6/e) (繁中版)
數字設計 — Verilog HDL、VHDL 和 SystemVerilog 實現, 6/e (簡中版)
-
其他版本:
Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog (6th Edition)
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商品描述
For introductory courses on digital design in an Electrical Engineering, Computer Engineering, or Computer Science department.
A clear and accessible approach to the basic tools, concepts, and applications of digital design
A modern update to a classic, authoritative text, Digital Design, 6th Edition teaches the fundamental concepts of digital design in a clear, accessible manner. The text presents the basic tools for the design of digital circuits and provides procedures suitable for a variety of digital applications. Like the previous editions, this edition of Digital Design supports a multimodal approach to learning, with a focus on digital design, regardless of language. Recognizing that three public-domain languages—Verilog, VHDL, and SystemVerilog—all play a role in design flows for today’s digital devices, the 6th Edition offers parallel tracks of presentation of multiple languages, but allows concentration on a single, chosen language.
商品描述(中文翻譯)
在電機工程、電腦工程或電腦科學系的入門課程中,提供了一種清晰易懂的方法來介紹數位設計的基本工具、概念和應用。
這是一本經典權威教材的現代更新版本,《數位設計》第六版以清晰易懂的方式介紹了數位設計的基本概念。本書提供了設計數位電路的基本工具,並提供了適用於各種數位應用的程序。與之前的版本一樣,本版《數位設計》支持多模式學習方法,專注於數位設計,無論使用何種語言。鑒於Verilog、VHDL和SystemVerilog這三種公共領域語言在當今數位設備的設計流程中都扮演著重要角色,《第六版》提供了多種語言的並行呈現方式,但也允許專注於單一選定的語言。
目錄大綱
Preface
1 Digital Systems and Binary Numbers
1.1 Digital Systems
1.2 Binary Numbers
1.3 Number-Base Conversions
1.4 Octal and Hexadecimal Numbers
1.5 Complements of Numbers
1.6 Signed Binary Numbers
1.7 Binary Codes
1.8 Binary Storage and Registers
1.9 Binary Logic
2 Boolean Algebra and Logic Gates
2.1 Introduction
2.2 Basic Definitions
2.3 Axiomatic Definition of Boolean Algebra
2.4 Basic Theorems and Properties of Boolean Algebra
2.5 Boolean Functions
2.6 Canonical and Standard Forms
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuits
3 Gate-Level Minimization
3.1 Introduction
3.2 The Map Method
3.3 Four-Variable K-Map
3.4 Product-of-Sums Simplification
3.5 Don’t-Care Conditions
3.6 NAND and NOR Implementation
3.7 Other Two-Level Implementations
3.8 Exclusive-OR Function
3.9 Hardware Description Languages (HDLs)
4 Combinational Logic
4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis of Combinational Circuits
4.4 Design Procedure
4.5 Binary Adder—Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL Models of Combinational Circuits
5 Synchronous Sequential Logic
5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 Synthesizable HDL Models of Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
6 Registers and Counters
6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL Models of Registers and Counters
7 Memory and Programmable Logic
7.1 Introduction
7.2 Random-Access Memory
7.3 Memory Decoding
7.4 Error Detection and Correction
7.5 Read-Only Memory
7.6 Programmable Logic Array
7.7 Programmable Array Logic
7.8 Sequential Programmable Devices
8 Design at the Register Transfer Level
8.1 Introduction
8.2 Register Transfer Level (RTL) Notation
8.3 RTL descriptions VERILOG (Edge- and Level-Sensitive Behaviors)
8.4 Algorithmic State Machines (ASMs)
8.5 Design Example (ASMD Chart)
8.6 HDL Description of Design Example
8.7 Sequential Binary Multiplier
8.8 Control Logic
8.9 HDL Description of Binary Multiplier
8.10 Design with Multiplexers
8.11 Race-Free Design (Software Race Conditions)
8.12 Latch-Free Design (Why Waste Silicon?)
8.13 System Verilog–An Introduction
9 Laboratory Experiments with Standard ICs and FPGAs
9.1 Introduction to Experiments
9.2 Experiment 1: Binary and Decimal Numbers
9.3 Experiment 2: Digital Logic Gates
9.4 Experiment 3: Simplification of Boolean Functions
9.5 Experiment 4: Combinational Circuits
9.6 Experiment 5: Code Converters
9.7 Experiment 6: Design with Multiplexers
9.8 Experiment 7: Adders and Subtractors
9.9 Experiment 8: Flip-Flops
9.10 Experiment 9: Sequential Circuits
9.11 Experiment 10: Counters
9.12 Experiment 11: Shift Registers
9.13 Experiment 12: Serial Addition
9.14 Experiment 13: Memory Unit
9.15 Experiment 14: Lamp Handball
9.16 Experiment 15: Clock-Pulse Generator
9.17 Experiment 16: Parallel Adder and Accumulator
9.18 Experiment 17: Binary Multiplier
9.19 HDL Simulation Experiments and Rapid Prototyping with FPGAs
10 Standard Graphic Symbols
10.1 Rectangular-Shape Symbols
10.2 Qualifying Symbols
10.3 Dependency Notation
10.4 Symbols for Combinational Elements
10.5 Symbols for FlipFlops
10.6 Symbols for Registers
10.7 Symbols for Counters
10.8 Symbol for RAM
Appendix
Answers to Selected Problems
Index
目錄大綱(中文翻譯)
前言
1 數位系統和二進制數字
1.1 數位系統
1.2 二進制數字
1.3 數字進制轉換
1.4 八進制和十六進制數字
1.5 數字的補數
1.6 有符號二進制數字
1.7 二進制編碼
1.8 二進制存儲和寄存器
1.9 二進制邏輯
2 布林代數和邏輯閘
2.1 簡介
2.2 基本定義
2.3 布林代數的公理定義
2.4 布林代數的基本定理和性質
2.5 布林函數
2.6 正規和標準形式
2.7 其他邏輯運算
2.8 數字邏輯閘
2.9 集成電路
3 閘級最小化
3.1 簡介
3.2 圖法方法
3.3 四變量K-圖
3.4 积和式簡化
3.5 不關心條件
3.6 NAND和NOR實現
3.7 其他二級實現
3.8 异或函數
3.9 硬件描述語言(HDL)
4 組合邏輯
4.1 簡介
4.2 組合電路
4.3 組合電路的分析
4.4 設計過程
4.5 二進制加減器
4.6 十進制加法器
4.7 二進制乘法器
4.8 大小比較器
4.9 解碼器
4.10 編碼器
4.11 多路器
4.12 組合電路的HDL模型
5 同步時序邏輯
5.1 簡介
5.2 時序電路
5.3 存儲元件:鎖存器
5.4 存儲元件:觸發器
5.5 鍛鍊時序電路的分析
5.6 可合成的時序電路的HDL模型
5.7 狀態簡化和分配
5.8 設計過程
6 寄存器和計數器
6.1 寄存器
6.2 移位寄存器
6.3 級聯計數器
6.4 同步計數器
6.5 其他計數器
6.6 寄存器和計數器的HDL模型
7 存儲器和可編程邏輯
7.1 簡介
7.2 隨機存取存儲器
7.3 存儲器解碼
7.4 錯誤檢測和修正
7.5 只讀存儲器
7.6 可編程邏輯陣列
7.7 可編程陣列邏輯
7.8 串行可編程設備
8 寄存器傳輸級設計
8.1 簡介
8.2 寄存器傳輸級(RTL)表示法
8.3 RTL描述VERILOG(邊緣和電平敏感行為)
8.4 算法狀態機(ASMs)
8.5 設計示例(ASMD圖)
8.6 設計示例的HDL描述
8.7 串行二進制乘法器
8.8 控制邏輯
8.9 二進制乘法器的HDL描述
8.10 使用多路器進行設計
8.11 無競爭設計(軟件競爭條件)
8.12 無鎖存器設計(為什麼浪費硅)
8.13 System Verilog-簡介
9 使用標準IC和FPGA進行實驗
9.1 實驗簡介
9.2 實驗1:二進制和十進制數字
9.3 實驗2:數字邏輯閘
9.4 實驗3:布林函數簡化
9.5 實驗4:組合電路
9.6 實驗5:編碼器
9.7 實驗6:使用多路器進行設計
9.8 實驗7:加法器和減法器
9.9 實驗8:觸發器
9.10 實驗9:時序電路
9.11 實驗10:計數器
9.12 實驗11:移位寄存器
9.13 實驗12:串行加法
9.14 實驗13:存儲器單元
9.15 實驗14:燈