Modular Low-Power, High-Speed CMOS Analog-To-Digital Converter for Embedded Systems

Keh-La Lin, Armin Kemna, Bedrich J. Hosticka

Modular Low-Power, High-Speed CMOS Analog-To-Digital Converter for Embedded Systems
  • 出版商: Springer
  • 出版日期: 2003-04-30
  • 售價: $1,600
  • 貴賓價: 9.8 折 $1,568
  • 語言: 英文
  • 頁數: 254
  • 裝訂: Hardcover
  • ISBN: 1402073801
  • ISBN-13: 9781402073809
  • 相關分類: CMOS、嵌入式系統

    • 下單後立即進貨 (約5~7天)

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Description

One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications.

Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

Table of contents
Foreword. List of Figures. List of Tables.
1: Introduction. 1.1. Motivation. 1.2. Organization of the Book.
2: Analog-to-Digital Conversion. 2.1. Concepts of A/D Conversion and D/A Conversion. 2.2. Sampling Theorem of the A/D Conversion. 2.3. Quantization Process of the A/D conversion. 2.4. Performance of A/D Converters. 2.5. Topologies and Architectures of High-Speed A/D Converters. 2.6. Problems of Embedded System with A/D Converter. 2.7. Summary.
3: Components for CMOS Folding and Interpolating A/D Converters. 3.1. Subsystem: Sample-and-Hold Amplifier. 3.2. High-Speed Operational Transconductance Amplifier. 3.3. Subsystem: Fine Converter. 3.4. Subsystem: Coarse Converter. 3.5. Comparator Stage. 3.6. Digital Signal Processing: Error Correction. 3.7. Digital Signal Processing: Algorithm for Binary Coding. 3.8. Subsystem: Synchronization.
4: Architecture and Design of CMOS Folding and Interpolating A/D Converters. 4.1. Introduction. 4.2. Architecture Optimization. 4.3. Design and Implementation of the 10-Bit Folding and Interpolating A/D Converter. 4.4. Architectural Scalability of the Folding and Interpolating A/D Converter. 4.5. Architecture Analysis for the 10-Bit Folding and Interpolating A/D Converter. 4.6. Architectural Hard Scaling. 4.7. Summary.
5: Physical Design of Low-Power, High Embedded CMOS A/D Converter. 5.1. Power Supply Network. 5.2. Reference Voltage Network. 5.3. Noise Coupling. 5.4. Summary of Recommended Design Practices for Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems.
6: Evaluation and Measurements. 6.1. Methodology for Analog Measurement. 6.2. Methodology for Digital Measurement. 6.3. Measurement Results. 6.4. Summary.
7: General Conclusions and Outlook.
Appendix A: Analysis for Small Signal Operation.
Appendix B: Source Codes for Binary Coding.
Appendix C: Test Results: Folding ADC vs. AD9203.
Symbols, Conventions, Notations, and Abbreviations.
Index. Bibliography.

商品描述(中文翻譯)

描述

微電子學的主要趨勢之一是朝向集成系統設計，即系統單晶片（SoC）或系統單晶片（SoS）。由於這一發展，混合信號電路的設計技術比以往更加重要。在其他設備中，模數轉換器和數模轉換器是模擬和數字世界之間的兩個橋樑。此外，低功耗設計技術是嵌入式系統的主要問題之一，特別是對於手持應用。

《嵌入式系統的模塊化低功耗、高速CMOS模數轉換器》旨在設計低功耗、高速模數轉換器，使用標準CMOS技術進行處理。此外，本書還涵蓋了集成在SoC中的A/D轉換器的物理集成問題，即基板串擾和參考電壓網絡設計。

目錄

前言。圖表清單。
1：引言。1.1。動機。1.2。本書組織。
2：模擬數字轉換。2.1。模擬數字轉換和數字模擬轉換的概念。2.2。模擬數字轉換的取樣定理。2.3。模擬數字轉換的量化過程。2.4。模擬數字轉換器的性能。2.5。高速模擬數字轉換器的拓撲和架構。2.6。嵌入式系統與A/D轉換器的問題。2.7。總結。
3：CMOS折疊和插值A/D轉換器的組件。3.1。子系統：採樣保持放大器。3.2。高速運算跨導放大器。3.3。子系統：精細轉換器。3.4。子系統：粗轉換器。3.5。比較器階段。3.6。數字信號處理：錯誤校正。3.7。數字信號處理：二進制編碼算法。3.8。子系統：同步。
4：CMOS折疊和插值A/D轉換器的架構和設計。4.1。介紹。4.2。架構優化。4.3。10位折疊和插值A/D轉換器的設計和實現。4.4。折疊和插值A/D轉換器的架構可擴展性。4.5。10位折疊和插值A/D轉換器的架構分析。4.6。架構硬擴展。4.7。總結。
5：低功耗、高嵌入式CMOS A/D轉換器的物理設計。5.1。電源供應網絡。5.2。參考電壓網絡。5.3。噪聲耦合。5.4。低功耗、高速CMOS模數轉換器的嵌入式系統推薦設計實踐總結。
6：評估和測量。6.1。模擬測量方法論。

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