Embedded System Design: Modeling, Synthesis and Verification (Hardcover)
暫譯: 嵌入式系統設計：建模、合成與驗證（精裝版）

<內容簡介>

*Offers numerous practical examples for professionals
*Includes case examples on industrial strength and practical standards
*Covers the state-of-the-art verification methods and emerging verification techniques for system level design
*Provides detailed descriptions of design techniques for various embedded software and hardware components
*Describes system design flows and design methodology from system specification to prototyping

Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail:

. System modeling at different abstraction levels

. Model-based system design

. Hardware/Software codesign

. Software and Hardware component synthesis

. System verification

This book is for groups within the embedded system community: students in courses on embedded systems, embedded application developers, system designers and managers, CAD tool developers, design automation, and system engineering.

 <章節目錄>

Preface

Acknowledgments

List of Figures

List of Tables

1. INTRODUCTION

1.1 System-Design Challenges
1.2 Abstraction Levels
1.2.1 Y-Chart
1.2.2 Processor-Level Behavioral Model
1.2.3 Processor-level structural model
1.2.4 Processor-level synthesis
1.2.5 System-Level Behavioral Model
1.2.6 System Structural Model
1.2.7 System Synthesis
1.3 System Design Methodology
1.3.1 Missing semantics
1.3.2 Model Algebra
1.4 System-Level Models
1.5 Platform Design
1.6 System Design Tools
1.7 Summary

2. SYSTEM DESIGN METHODOLOGIES

2.1 Bottom-up Methodology
2.2 Top-down Methodology
2.3 Meet-in-the-middle Methodology
2.4 Platform Methodology
2.5 FPGA Methodology
2.6 System-level Synthesis
2.7 Processor Synthesis
2.8 Summary

3. MODELING

3.1 Models of Computation
3.1.1 Process-Based Models
3.1.2 State-Based Models
3.2 System Design Languages
3.2.1 Netlists and Schematics
3.2.2 Hardware-Description Languages
3.2.3 System-Level Design Languages
3.3 System Modeling
3.3.1 Design Process
3.3.2 Abstraction Levels
3.4 Processor Modeling
3.4.1 Application Layer
3.4.2 Operating System Layer
3.4.3 Hardware Abstraction Layer
3.4.4 Hardware Layer
3.5 Communication Modeling
3.5.1 Application Layer
3.5.2 Presentation Layer
3.5.3 Session Layer
3.5.4 Network Layer
3.5.5 Transport Layer
3.5.6 Link Layer
3.5.7 Stream Layer
3.5.8 Media Access Layer
3.5.9 Protocol and Physical Layers
3.6 System Models
3.6.1 Speci cation Model
3.6.2 Network TLM
3.6.3 Protocol TLM
3.6.4 Bus Cycle-Accurate Model (BCAM)
3.6.5 Cycle-Accurate Model (CAM)
3.7 Summary

4. SYSTEM SYNTHESIS

4.1 System Design Trends
4.2 TLM Based Design
4.3 Automatic TLM Generation
4.3.1 Application Modeling
4.3.2 Platform De nition
4.3.3 Application to Platform Mapping
4.3.4 TLM Based Performance Estimation
4.3.5 TLM Semantics
4.4 Automatic Mapping
4.4.1 GSM Encoder Application
4.4.2 Application Pro ling
4.4.3 Load Balancing Algorithm
4.4.4 Longest Processing Time Algorithm
4.5 Platform Synthesis
4.5.1 Component data models
4.5.2 Platform Generation Algorithm
4.5.3 Cycle Accurate Model Generation
4.5.4 Summary

5. SOFTWARE SYNTHESIS

5.1 Preliminaries
5.1.1 Target Languages for Embedded Systems
5.1.2 RTOS
5.2 Software Synthesis Overview
5.2.1 Example Input TLM
5.2.2 Target Architecture
5.3 Code Generation
5.4 Multi-Task Synthesis
5.4.1 RTOS-based Multi-Tasking
5.4.2 Interrupt-based Multi-Tasking
5.5 Internal Communication
5.6 External Communication
5.6.1 Data Formatting
5.6.2 Packetization
5.6.3 Synchronization
5.6.4 Media Access Control
5.7 Startup Code
5.8 Binary Image Generation
5.9 Execution
5.10Summary

6. HARDWARE SYNTHESIS

6.1 RTL Architecture
6.2 Input Models
6.2.1 C-code speci cation
6.2.2 Control-Data Flow Graph speci cation
6.2.3 Finite State Machine with Data speci cation
6.2.4 RTL speci cation
6.2.5 HDL speci cation
6.3 Estimation and Optimization
6.4 Register Sharing
6.5 Functional Unit Sharing
6.6 Connection Sharing
6.7 Register Merging
6.8 Chaining and Multi-Cycling
6.9 Functional-Unit Pipelining
6.10Datapath Pipelining
6.11Control and Datapath Pipelining
6.12Scheduling
6.12.1RC scheduling
6.12.2TC scheduling
6.13Interface Synthesis
6.14Summary

7. VERIFICATION

7.1 Simulation Based Methods
7.1.1 Stimulus Optimization
7.1.2 Monitor Optimization
7.1.3 SpeedUp Techniques
7.1.4 Modeling Techniques
7.2 Formal Veri cation Methods
7.2.1 Logic Equivalence Checking
7.2.2 FSM Equivalence Checking
7.2.3 Model Checking
7.2.4 Theorem Proving
7.2.5 Drawbacks of Formal Veri cation
7.2.6 Improvements to Formal Veri cation Methods
7.2.7 Semi-formal Methds: Symbolic Simulation
7.3 Comparative Analysis of Veri cation Methods
7.4 System Level Veri cation
7.4.1 Formal Modeling
7.4.2 Model Algebra
7.4.3 Veri cation by Correct Re nement
7.5 Summary

8. EMBEDDED DESIGN PRACTICE

8.1 System Level Design Tools
8.1.1 Academic Tools
8.1.2 Commercial Tools
8.1.3 Outlook
8.2 Embedded Software Design Tools
8.2.1 Academic Tools
8.2.2 Commercial Tools
8.2.3 Outlook
8.3 Hardware Design Tools
8.3.1 Academic Tools
8.3.2 Commercial Tools
8.3.3 Outlook
8.4 Case Study
8.4.1 Embedded System Environment
8.4.2 Design Driver: MP3 Decoder
8.4.3 Results
8.5 Summary

References