電腦組成與設計:硬件/軟件接口 (原文版) (Computer Organization and Design RISC-V Edition: The Hardware Software Interface)

[美] 戴維·A. 帕特森(David A. Patterson) 約翰·L. 亨尼斯(John L. Hennessy) 著

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本書採用RISC-V體系結構,講解硬件技術,彙編語言,計算機算術運算,流水線,存儲器層次結構以及I / O的基本原理。新內容涵蓋平板電腦,雲基礎設施,ARM(移動計算設備)以及x86(雲計算)體系結構,新實例包括Intel Core i7 ,ARM Cortex-A53以及NVIDIA Fermi GPU。本書適合作為高等院校計算機專業的教材,也適合廣大專業技術人員參考。

作者簡介

戴維·A。帕特森(David A.Patterson),Patte rson與Hennessy共同榮獲了2017年度“圖靈獎”,以表彰他們在計算機體系結構領域的開創性貢獻.Patte rson現為Google傑出工程師,之前為加州大學伯克利分校教授。他曾任ACM主席一職。目前是ACM和IEEE會士,美國藝術與科學院和計算機歷史博物館院士,並入選了美國國家工程院,國家科學院和矽谷工程名人堂。他領導了RISCI的設計與實現工作,並且是RAID項目的領導者。

目錄大綱

CHAPTERS 
1 Computer Abstractions and Technology 
1.1 Introduction 
1.2 Eight Great Ideas in Computer Architecture 
1.3 Below Your Program 
1.4 Under the Covers 
1.5 Technologies for Building Processors and Memory 
1.6 Performance 
1.7 The Power Wall 
1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 
1.9 Real Stuff: Benchmarking the Intel Core i7 
1.10 Fallacies and Pitfalls 
1.11 Concluding Remarks 
1.12 Historical Perspective and Further Reading 
1.13 Exercises 
2 Instructions: Language of the Computer 
2.1 Introduction 
2.2 Operations of the Computer Hardware 
2.3 Operands of the Computer Hardware 
2.4 Signed and Unsigned Numbers 
2.5 Representing Instructions in the Computer 
2.6 Logical Operations 
2.7 Instructions for Making Decisions 
2.8 Supporting Procedures in Computer Hardware 
2.9 Communicating with People 
2.10 RISC-V Addressing for Wide Immediates and Addresses 
2.11 Parallelism and Instructions: Synchronization 
2.12 Translating and Starting a Program 
2.13 A C Sort Example to Put it All Together 
2.14 Arrays versus Pointers 
2.15 Advanced Material: Compiling C and Interpreting lava 
2.16 Real Stuff: MIPS Instructions 
2.17 Real Stuff: x86 Instructions 
2.18 Real Stuff: The Rest of the RISC-V Instruction Set 
2.19 Fallacies and Pitfalls 
2.20 Concluding Remarks 
2.21 Historical Perspective and Further Reading 
2.22 Exercises 
3 Arithmetic for Computers 
3.1 Introduction 
3.2 Addition and Subtraction 
3.3 Multiplication 
3.4 Division 
3.5 Floating Point 
3.6 Parallelism and Computer Arithmetic: Subword Parallelism 
3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86 
3.8 Going Faster: Subword Parallelism and Matrix Multiply 
3.9 Fallacies and Pitfalls 
3.10 Concluding Remarks 
3.11 Historical Perspective and Further Reading 
3.12 Exercises 
4 The Processor 
4.1 Introduction 
4.2 Logic Design Conventions 
4.3 Building a Datapath 
4.4 A Simple Implementation Scheme 
4.5 An Overview of Pipelining 
4.6 Pipelined Datapath and Control 
4.7 Data Hazards: Forwarding versus Stalling 
4.8 Control Hazards 
4.9 Exceptions 
4.10 Parallelism via Instructions 
4.11 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Pipelines 
4.12 Going Faster: Instruction-Level Parallelism and Matrix Multiply 
4.13 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 
4.14 Fallacies and Pitfalls 
4.15 Concluding Remarks 
4.16 Historical Perspective and Further Reading 
4.17 Exercises 
5 Large and Fast: Exploiting Memory Hierarchy 
5.1 Introduction 
5.2 Memory Technologies 
5.3 The Basics of Caches 
5.4 Measuring and Improving Cache Performance 
5.5 Dependable Memory Hierarchy 
5.6 Virtual Machines 
5.7 Virtual Memory 
5.8 A Common Framework for Memory Hierarchy 
5.9 Using a Finite-State Machine to Control a Simple Cache 
5.10 Parallelism and Memory Hierarchy: Cache Coherence 
5.11 Parallelism and Memory Hierarchy: Redundant Arrays ot Inexpensive Disks 
5.12 Advanced Material: Implementing Cache Controllers 
5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory Hierarchies 
5.14 Real Stuff: The Rest of the RISC-V System and Special Instructions 
5.15 Going Faster: Cache Blocking and Matrix Multiply 
5.16 Fallacies and Pitfalls 
5.17 Concluding Remarks 
5.18 Historical Perspective and Further Reading 
5.19 Exercises 
6 Parallel Processors from Client to Cloud 
6.1 Introduction 
6.2 The Difficulty of Creating Parallel Processing Programs 
6.3 SISD, MIMD, SIMD