Digital Logic Design Using Verilog: Coding and RTL Synthesis 2nd ed. 2022 Edition
Taraate, Vaibbhav
- 出版商: Springer
- 出版日期: 2021-11-01
- 售價: $5,160
- 貴賓價: 9.5 折 $4,902
- 語言: 英文
- 頁數: 629
- 裝訂: Hardcover - also called cloth, retail trade, or trade
- ISBN: 9811631980
- ISBN-13: 9789811631986
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相關分類:
Verilog、邏輯設計 Logic-design
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其他版本:
Digital Logic Design Using Verilog: Coding and RTL Synthesis 2nd ed. 2022 Edition
海外代購書籍(需單獨結帳)
相關主題
商品描述
Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.
作者簡介
Vaibbhav Taraate is an entrepreneur and mentor at "1 Rupee S T". He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
