Advanced Chip Design, Practical Examples in Verilog (Paperback)
Mr Kishore K Mishra
- 出版商: CreateSpace Independ
- 出版日期: 2013-04-16
- 售價: $1,760
- 貴賓價: 9.5 折 $1,672
- 語言: 英文
- 頁數: 728
- 裝訂: Paperback
- ISBN: 1482593335
- ISBN-13: 9781482593334
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相關分類:
Verilog
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相關翻譯:
Verilog 高級數字系統設計技術與實例分析 (簡中版)
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商品描述
Designing a complex ASIC/SoC is similar to learning a language well and then creating a masterpiece using experience, imagination, and creativity. Digital design starts with RTL such as Verilog or VHDL, but it is only the beginning. A complete designer needs to have a good understanding of the Verilog language, digital design techniques, system architecture, IO protocols, and hardware-software interaction that I call the five rings of chip design.
This book is the result of 20 years of experience and passion for chip design, love for the Verilog language, three years of focused research, and a genuine desire to share the practical design world with students and practicing engineers. I sincerely believe that you are not only going to get a jump-start, but also keep using this book for the rest of your career. A must digital design and Verilog book and a trusted companion that covers the five rings with plenty of real-world Verilog examples.
The book is broadly divided into two sections - chapters 1 through 10, focusing on the digital design aspects and chapters 11 through 20, focusing on the system aspects of chip design.
Chapter 3 focuses on the synthesizable Verilog constructs, with examples on reusable design (parameterized design, functions, and generate structure). Chapter 5 describes the basic concepts in digital design - logic gates, truth table, De Morgan's theorem, set-up and hold time, edge detection, and number system. Chapter 6 goes into details of digital design explaining larger building blocks such as LFSR, scrambler/descramblers, parity, CRC, Error Correction Codes (ECC), Gray encoding/decoding, priority encoders, 8b/10b encoding, data converters, and synchronization techniques.
Chapter 7 and 8 bring in advanced concepts in chip design and architecture - clocking and reset strategy, methods to increase throughput and reduce latency, flow-control mechanisms, pipeline operation, out-of-order execution, FIFO design, state machine design, arbitration, bus interfaces, linked list structure, and LRU usage and implementation.
Chapter 9 and 10 describe how to build and design ASIC/SoC. It talks about chip micro-architecture, partitioning, datapath, control logic design, and other aspects of chip design such as clock tree, reset tree, and EEPROM. It also covers good design practices, things to avoid and adopt, and best practices for high-speed design. The second part of the book is devoted to System architecture, design, and IO protocols.
Chapter 11 talks about memory, memory hierarchy, cache, interrupt, types of DMA and DMA operation. There is Verilog RTL for a typical DMA controller design that explains the scatter-gather DMA concept. Chapter12 describes hard drive, solid-state drive, DDR operation, and other parts of a system such as BIOS, OS, drivers, and their interaction with hardware. Chapter 13 describes embedded systems and internal buses such as AHB, AXI used in embedded design. It describes the concept of transparent and non-transparent bridging.
Chapter 14 and chapter 15 bring in practical aspects of chip development - testing, DFT, scan, ATPG, and detailed flow of the chip development cycle (Synthesis, Static timing, and ECO). Chapter 16 and chapter 17 are on power saving and power management protocols. Chapter 16 has a detailed description of various power savings techniques (frequency variation, clock gating, and power well isolation).
Chapter 17 talks about Power Management protocols such as system S states, CPU C states, and device D states. Chapter 18 explains the architecture behind serial-bus technology, PCS, and PMA layer. It describes clocking architecture and advanced concepts such as elasticity FIFO, channel bonding (deskewing), link aggregation, and lane reversal. Chapter 19 and 20 are devoted to serial bus protocols (PCI Express, Serial ATA, USB, Thunderbolt, and Ethernet) and their operation.
Appendix B covers FPGA basics, and Appendix D covers SystemVerilog Assertions (SVA).
商品描述(中文翻譯)
設計一個複雜的ASIC/SoC就像是學習一門語言並利用經驗、想像力和創造力創作一個傑作。數位設計從RTL(如Verilog或VHDL)開始,但這只是個開始。一個完整的設計師需要對Verilog語言、數位設計技術、系統架構、IO協議和硬體軟體互動有良好的理解,我稱之為「晶片設計的五個環」。
這本書是20年經驗和對晶片設計的熱情、對Verilog語言的熱愛、三年專注研究和真誠的願望與學生和實踐工程師分享實際設計世界的結果。我真誠地相信,你不僅會得到一個快速入門,還會在你的職業生涯中一直使用這本書。這是一本必讀的數位設計和Verilog書籍,也是一個值得信賴的伴侶,其中包含許多實際的Verilog範例。
這本書大致分為兩個部分-第1章到第10章關注數位設計方面,第11章到第20章關注晶片設計的系統方面。
第3章著重於可合成的Verilog結構,並提供可重複使用的設計示例(參數化設計、函數和生成結構)。第5章描述了數位設計的基本概念-邏輯閘、真值表、德摩根定理、設置和保持時間、邊緣檢測和數字系統。第6章詳細解釋了數位設計的更大的構建塊,如LFSR、混淆器/解混淆器、奇偶校驗、CRC、錯誤校正碼(ECC)、格雷編碼/解碼、優先編碼器、8b/10b編碼、數據轉換器和同步技術。
第7章和第8章介紹了晶片設計和架構的高級概念-時鐘和重置策略、增加吞吐量和減少延遲的方法、流量控制機制、流水線操作、無序執行、FIFO設計、狀態機設計、仲裁、匯流排接口、鏈表結構和LRU使用和實現。
第9章和第10章描述了如何構建和設計ASIC/SoC。它談到了晶片微架構、分割、數據通路、控制邏輯設計以及晶片設計的其他方面,如時鐘樹、重置樹和EEPROM。它還涵蓋了良好的設計實踐、應避免和採用的事項,以及高速設計的最佳實踐。本書的第二部分專注於系統架構、設計和IO協議。
第11章講述了記憶體、記憶體層次結構、快取、中斷、不同類型的DMA和DMA操作。書中提供了一個典型DMA控制器設計的Verilog RTL,解釋了分散收集DMA的概念。第12章描述了硬碟、固態硬碟、DDR操作以及系統的其他部分,如BIOS、作業系統、驅動程式及其與硬體的互動。第13章描述了嵌入式系統和內部匯流排,如在嵌入式設計中使用的AHB、AXI。它還描述了透明和非透明橋接的概念。
第14章和第15章介紹了實際的應用方面。