System-on-Chip Test Architectures (Hardcover)(庫存書況書側皆有霉斑,不介意者再下單)

因年代較久,庫存書況書側皆有霉斑,不介意者在下單!!

Description

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Table of Contents

Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

因年代較久，庫存書況書側皆有霉斑，不介意者在下單!!

Description

現代電子測試已有超過40年的歷史。新技術的引入，尤其是90納米或更小幾何尺寸的納米技術，使半導體行業能夠跟上消費者對性能和容量需求的增加。因此，半導體測試成本一直在穩步增長，通常佔到今天整體產品成本的40%。本書是一本全面指南，介紹了新的VLSI測試和設計可測試性技術，讓學生、研究人員、DFT從業人員和VLSI設計師能夠快速掌握片上系統測試架構，用於數字、記憶體和類比/混合信號設計的測試調試和診斷。

Table of Contents

導論; 數字測試架構; 容錯設計; SOC/NOC測試架構; SIP測試架構; 延遲測試; 低功耗測試; 應對物理故障、軟錯誤和可靠性問題; 設計可製造性和良率; 設計調試和診斷; 基於軟體的自測試; FPGA測試; MEMS測試; 高速I/O接口; 類比和混合信號測試架構; RF測試; 納米技術趨勢的測試方面。