ESD: Design and Synthesis (Hardcover)

Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.

This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a ‘top-down' design approach.

Look inside for extensive coverage on:

• integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integration
• architecturing of mixed voltage, mixed signal, to RF design for ESD analysis
• floorplanning for peripheral and core I/O designs, and the implications on ESD and latchup
• guard ring integration for both a ‘bottom-up' and ‘top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to core
• classification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chip
• examples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart power
• practical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics

ESD: Design and Synthesis is a continuation of the author's series of books on ESD protection. It is an essential reference for: ESD, circuit, and semiconductor engineers; design synthesis team leaders; layout design, characterisation, floorplanning, test and reliability engineers; technicians; and groundrule and test site developers in the manufacturing and design of semiconductor chips.

It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, and manufacturing sciences, and on courses involving the design of ESD devices, chips and systems. This book offers a useful insight into the issues that confront modern technology as we enter the nano-electronic era.

靜電放電（ESD）在從微電子到納米電子的技術規模下，持續對半導體元件和系統產生影響。

本書從整體芯片ESD設計綜合的角度研究了電氣過壓、ESD和閂鎖現象。它從一個通用的角度提供了對ESD保護網絡的整合的清晰洞察，然後通過具體的技術、電路和芯片示例進行了說明。獨特的是，本書從一個“自上而下”的設計方法論來涵蓋半導體芯片的整合問題和ESD網絡的平面布局。

內容豐富，包括：

- 在DRAM、SRAM、CMOS影像處理芯片、微處理器、模擬產品、射頻元件中整合核心、電源總線和信號引腳，以及這種整合對ESD設計和整合的影響。
- 為ESD分析設計混合電壓、混合信號和射頻設計。
- 為外圍和核心I/O設計進行平面布局，以及對ESD和閂鎖的影響。
- 针对I/O防護環、ESD防護環、I/O到I/O和I/O到核心的“自下而上”和“自上而下”方法進行防護環整合。
- 對ESD電源夾和ESD信號引腳電路的分類，以及如何根據給定的半導體芯片做出正確選擇的方法。
- 對所討論的最先進技術（包括CMOS、BiCMOS、絕緣體上硅（SOI）、雙極技術、高壓CMOS（HVCMOS）、射頻CMOS和智能功率）的ESD設計示例。
- 了解ESD電路電源分配、地規則制定、內部匯流排分配、電流路徑分析和質量指標的實用方法。

《ESD：設計與綜合》是作者關於ESD保護的系列書籍的延續。它是ESD、電路和半導體工程師、設計綜合團隊負責人、佈局設計、特性化、平面布局、測試和可靠性工程師、技術人員以及半導體芯片製造和設計中的地規則和測試場地開發人員的必備參考資料。

對於電氣工程、半導體科學和製造科學的研究生和本科生，以及涉及ESD器件、芯片和系統設計的課程，本書提供了有用的洞察，幫助理解現代技術在進入納米電子時代時所面臨的問題。