Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)

Sridhar Gangadharan

  • 出版商: Springer
  • 出版日期: 2015-06-23
  • 售價: $3,970
  • 貴賓價: 9.5$3,772
  • 語言: 英文
  • 頁數: 256
  • 裝訂: Paperback
  • ISBN: 1489989161
  • ISBN-13: 9781489989161
  • 海外代購書籍(需單獨結帳)

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商品描述

This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

商品描述(中文翻譯)

這本書是一本關於集成電路設計中時序約束的實用指南。讀者將學習如何正確指定時序要求,以最大化其集成電路設計的性能。內容包括時序約束所影響的設計流程的關鍵方面,包括合成、靜態時序分析、佈局和布線。詳細解釋了指定時序要求所需的概念,並將其應用於設計流程中的特定階段,全部在Synopsys Design Constraints(SDC)的框架下進行,這是業界領先的約束指定格式。