Introduction to Logic Synthesis using Verilog HDL (原版:9781598291063)
暫譯: 使用 Verilog HDL 的邏輯綜合入門

Reese/Thornton

Introduction to Logic Synthesis using Verilog HDL (原版:9781598291063)
  • 出版商: Morgan & Claypool
  • 出版日期: 2006-10-25
  • 售價: $1,500
  • 貴賓價: 9.5 折 $1,425
  • 語言: 英文
  • 頁數: 84
  • ISBN: 1598294040
  • ISBN-13: 9781598294040
  • 相關分類: Verilog

    • 海外代購書籍(需單獨結帳)

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商品描述

Description

Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.

商品描述(中文翻譯)

**描述**

《使用 Verilog HDL 的邏輯綜合入門》解釋了如何撰寫準確的 Verilog 敘述，以描述可以合成為具有理想特性的數位系統網路清單的數位系統。這本書包含了許多 Verilog 範例，從簡單的組合邏輯網路開始，逐步進入同步序列邏輯系統。書中也討論了在開發可合成的 Verilog HDL 時常見的陷阱，以及避免這些陷阱的方法。目標讀者是對數位邏輯原則有基本了解的任何人，想學習如何以允許自動合成的方式在 Verilog HDL 中建模數位系統。從業餘愛好者和本科生到資深專業人士，廣泛的讀者都會發現這本書引人入勝且易於接觸。這本書對材料進行了簡明的覆蓋，並包含許多範例，使讀者能夠快速生成高品質的可合成 Verilog 模型。

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