Static Timing Analysis for Nanometer Designs: A Practical Approach (Hardcover)

J. Bhasker, Rakesh Chadha

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商品描述

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.

The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.

This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

商品描述(中文翻譯)

這本書涵蓋了許多主題,包括單元時序和功率建模;互連建模和分析、延遲計算、串擾、噪音以及使用靜態時序分析進行晶片時序驗證。對於每個主題,本書提供了理論背景以及詳細的例子來闡述概念。

靜態時序分析的主題從驗證對於初學者有用的簡單模塊開始。然後,這些主題擴展到深入處理複雜的奈米設計,包括對於片上變異建模、時鐘閘控、半週期路徑以及DDR等源同步接口的時序的詳細處理。本書還涵蓋了串擾對時序和噪音的影響,以及分層設計方法的使用。

本書涉及CMOS邏輯閘、單元庫、時序弧、波形斜率、單元電容、時序建模、互連寄生和耦合、佈局前後的互連建模、延遲計算、內部路徑和IO接口的時序約束規範。還涵蓋了高級建模和分析概念,如奈米技術的受控電流源時序和噪音模型、功率建模(包括主動和漏電功率)、串擾時序和串擾故障計算、半週期和多週期路徑的驗證,以及同步接口。