VHDL Coding Styles and Methodologies, 2/e (Hardcover)
暫譯: VHDL 編碼風格與方法論，第2版 (精裝本)

VHDL Coding Styles and Methodologies, Second Edition is a follow-up book to the first edition of the same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy-to-read book that gave in-depth coverage of both the language and coding methodologies. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD, which also includes the GNU toolsite with EMACS language-sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity is kindly making available an evaluation version of Synplify, a very efficient, user-friendly and easy-to-use FPGA synthesis tool. Synplify provides a user with both the RTL and gate-level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool. VHDL Coding Styles and Methodologies, Second Edition is intended for professional engineers as well as students. It is organized in thirteen chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, leads the reader in the right direction from the beginning. CD INCLUDED VHDL Coding Styles and Methodologies, Second Edition includes a CD that contains + All code included in the book + GNU EMACS language-sensitive editor with VHDL, Verilog, and templates for other languages + GNU TSHELL tools that emulate Unix shell + Thirty-day evaluation of ModelSim VHDL compiler/simulator from Model Technology + Twenty-day evaluation of Synplify VHDL/Verilog FPGA synthesizer from Synplicity + VHDL template demonstrating the language syntax + VHDL '87 and VHDL '93 formal syntax in HTML format.