Network-on-Chip: The Next Generation of System-on-Chip Integration
暫譯: 片上網路:下一代系統單晶片整合
Santanu Kundu, Santanu Chattopadhyay
- 出版商: CRC
- 出版日期: 2017-07-26
- 售價: $2,850
- 貴賓價: 9.5 折 $2,708
- 語言: 英文
- 頁數: 388
- 裝訂: Paperback
- ISBN: 1138749354
- ISBN-13: 9781138749351
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其他版本:
Network-on-Chip: The Next Generation of System-on-Chip Integration (Hardcover)
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商品描述
Addresses the Challenges Associated with System-on-Chip Integration
Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.
Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.
This text comprises 12 chapters and covers:
- The evolution of NoC from SoC―its research and developmental challenges
- NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
- The router design strategies followed in NoCs
- The evaluation mechanism of NoC architectures
- The application mapping strategies followed in NoCs
- Low-power design techniques specifically followed in NoCs
- The signal integrity and reliability issues of NoC
- The details of NoC testing strategies reported so far
- The problem of synthesizing application-specific NoCs
- Reconfigurable NoC design issues
- Direction of future research and development in the field of NoC
Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.
商品描述(中文翻譯)
*解決系統單晶片整合相關的挑戰*
**網路晶片:系統單晶片整合的下一代** 探討了當前限制晶片間通訊效率的問題,並探索了網路晶片(Network-on-Chip, NoC),這是一個有前景的替代方案,讓設計者能夠透過在單一系統單晶片(System-on-Chip, SoC)上整合大量核心,來產生可擴展、可重用且高效能的通訊骨幹。本書提供了與基於 NoC 設計相關主題的基本概述:通訊基礎設施設計、通訊方法論、評估框架以及應用程式在 NoC 上的映射。它詳細說明了不同提議的 NoC 結構的設計與評估、低功耗技術、信號完整性與可靠性問題、應用映射、測試及未來趨勢。
本書利用已在產業和學術界實施的晶片範例,呈現了經過工業 CAD 工具實現驗證的元件完整架構設計。它描述了 NoC 的研究與發展,納入強化分析程序的理論證明,並包括在 NoC 設計與合成中使用的演算法。此外,它考慮了其他即將出現的 NoC 問題,如低功耗 NoC 設計、信號完整性問題、NoC 測試、重配置、合成及三維 NoC 設計。
*本書包含 12 章,涵蓋:*
- NoC 從 SoC 的演變——其研究與發展挑戰
- NoC 協定,詳細說明流量控制、可用的網路拓撲、路由機制、容錯、服務品質支持及網路介面的設計
- NoC 中的路由器設計策略
- NoC 架構的評估機制
- NoC 中的應用映射策略
- NoC 中專門遵循的低功耗設計技術
- NoC 的信號完整性與可靠性問題
- 迄今為止報告的 NoC 測試策略的細節
- 合成特定應用的 NoC 的問題
- 可重配置 NoC 設計問題
- NoC 領域未來研究與發展的方向
**網路晶片:系統單晶片整合的下一代** 涵蓋了與基於 NoC 設計相關的基本主題、技術及未來趨勢,適合工程師、學生、研究人員及其他對計算機架構、嵌入式系統和平行/分散式系統感興趣的業界專業人士使用。