Introduction to Advanced System-on-Chip Test Design and Optimization (Hardvover)

Description

Testing of Integrated Circuits is important to ensure the production of fault-free chips. However, testing is becoming cumbersome and expensive due to the increasing complexity of these ICs. Technology development has made it possible to produce chips where a complete system, with an enormous transistor count, operating at a high clock frequency, is placed on a single die - SOC (System-on-Chip). The device size miniaturization leads to new fault types, the increasing clock frequencies enforces testing for timing faults, and the increasing transistor count results in a higher number of possible fault sites. Testing must handle all these new challenges in an efficient manner having a global system perspective.

 

Test design is applied to make a system testable. In a modular core-based environment where blocks of reusable logic, the so called cores, are integrated to a system, test design for each core include: test method selection, test data (stimuli and responses) generation (ATPG), definition of test data storage and partitioning [off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST (Built-In Self-Test)], wrapper selection and design (IEEE std 1500), TAM (test access mechanism) design, and test scheduling minimizing a cost function whilst considering limitations and constraint. A system test design perspective that takes all the issues above into account is required in order to develop a globally optimized solution.

 

SOC test design and its optimization is the topic of this book. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.

 

Table of contents

Part I. Testing Concepts. Introduction. Design Flow. Design for Test. Boundary Scan.- Part II. SoC Design for Testability. System Modeling. Test Conflicts. Test Power Dissipation. Test Access Mechanism. Test Scheduling.- Part III. SoC Test Applications. A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. An Integrated Framework for the Design and Optimization of SoC Test Solutions. Efficient Test Solutions for Core-Based Designs. Integrating Core Selection in the System-On-Chip Test Solution Design-Flow. Defect-Aware Test Scheduling. An Integrated Technique for Test Vector Selection and Test Scheduling Under Ate Memory Depth Constraint.- Appendix 1. Benchmarks.- References.- Index.