Starter's Guide to Verilog 2001

Michael D. Ciletti

  • 出版商: Prentice Hall
  • 出版日期: 2003-09-19
  • 售價: $3,330
  • 貴賓價: 9.5$3,164
  • 語言: 英文
  • 頁數: 256
  • 裝訂: Paperback
  • ISBN: 0131415565
  • ISBN-13: 9780131415560
  • 相關分類: Verilog
  • 已絕版





For undergraduate courses in Advanced Digital Logic and Advanced Digital Design in departments of electrical engineering, computer engineering, and computer science.

Introducing the Verilog HDL in a brief format, this text presents a selected set of the changes the popular hardware underwent in its first revision—emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis.


Table of Contents:

1. Introduction to Digital Design Methodology.

2. Basic Concepts: Primitives, Data Types, and Operators in Verilog.

3. Modeling Structure with Verilog.

4. Modeling Behavior with Verilog.

5. Modeling Finite-State Mechanics and Datapath Controllers with Verilog.